1. Field of the Invention
Embodiments of the present invention relate generally to a semiconductor memory devices. More specifically, embodiments of the invention relate to a read operation for semiconductor memory devices, such as NAND/RAM memory devices.
This application claims priority to Korean Patent Application No. 2005-93011 filed Oct. 4, 2005, the subject matter of which is hereby incorporated by reference.
2. Discussion of Related Art
A great variety of semiconductor memory devices are used in contemporary electronic systems to store data. Semiconductor memory devices include a Random Access Memory (RAM) and a Read Only Memory (ROM). A RAM is a volatile memory device that loses stored data when its power is turned OFF. A ROM is a nonvolatile memory device that retains stored data even when its power is turned OFF.
RAM includes the Dynamic RAM (DRAM), Static RAM (SRAM), etc. ROM includes the programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), NAND flash memory, NOR flash memory, etc.
Regardless of the particular form of semiconductor memory device, stored data is retrieved from a semiconductor memory device using an operation generically referred to as a “read operation”.
Recently, a new type of semiconductor memory device (hereafter broadly referred to as a “NAND/RAM memory device”) has been actively investigated and developed that enjoys advantages commonly associated with both NAND flash memory and data RAM. That is, the NAND/RAM memory device is implemented with both NAND flash memory and data RAM sections integrated in a single memory device. During a program operation of the NAND/RAM memory device, data from an external circuit (hereafter generically referred to as a “host”) is first written into the data RAM and thereafter stored programmed into the NAND flash memory.
During a subsequent read operation, data stored in the NAND flash memory is output to the host via the data RAM in response to a read command received from the host. Thus, the NAN D/RAM memory device typically performs a read operation as follows. First, in the NAND flash memory, a page buffer senses data (e.g., page data) from a page of memory cells, and the sensed data is temporally stored in the page buffer. The sensed data in the page buffer is then transferred to the data RAM. The host then fetches data from the data RAM in synchronization with a clock signal.
As with any memory device, the NAND/RAM memory device must be able to program data or have data read from it in a time period defined by the host. As the operation speed of various hosts is increased, this requirement has begun to stress the operating capabilities of conventional NAND/RAM memory devices.
For example, the ultimate speed of a read operation performed in a NAND/RAM memory device is limited by the time it takes to sense data from the memory cell array of the NAND memory using a page buffer.
FIG. (FIG.) 1 is a timing diagram illustrating a read operation for a conventional NAND/RAM memory device. Referring to FIG. 1, in order to provide requested data to the host, the NAND/RAM memory device must perform a sensing operation carried out during a sense time tS, a transfer operation during a transfer time tT, and a read-out operation during a readout time tR. The read-out operation is performed responsive to a clock signal CLK received from the host. Under these circumstances, if the frequency of the host clock signal CLK is increased, the readout time tR must be correspondingly decreased.
Unfortunately, although the frequency of the host clock signal CLK increases, the overall read operation speed for the NAND/RAM memory device is not increased, because the overall read operation speed is a function of the fixed sensing time tS. Thus, the conventional NAND/RAM memory device exhibits a read operation speed insensitive to changes in the host clock signal CLK.